1. Field of the Invention
The present invention relates to a memory device of a dynamic type such as a dynamic random access memory (DRAM), a refresh control circuit to be used for the memory device, and a refresh method.
2. Description of the Related Art
A memory device of a dynamic type has been conventionally used as a memory device applicable to a computer apparatus and the like. As a typical memory device, a semiconductor memory device such as the so-called DRAM is known.
FIG. 9 shows an example of the schematic configuration of a memory cell 900. The memory cell 900 uses a transistor element 901 as a switching element. The turning on and off of the transistor element 901 is controlled through a word line 903. Data (charge) writing and data reading of the memory cell 900 are set to be controlled through a bit line 902. The charge quantity held in a capacitor (an electric capacity unit) 904 of the memory cell 900 is gradually decreased at every performance of a read operation, or owing to various kinds of parasitic capacitance and natural discharge. When the charge quantity becomes smaller than a fixed value, the content stored in the capacitor 904 is lost (or volatilized). Accordingly, such a memory device of a dynamic type as the DRAM needs the so-called refresh operation, by which charge held in the memory cell 900 till then is amplified and is re-written.
A typical example of this kind of dynamic-type memory device, a DRAM 800, as schematically simplified to be shown in FIG. 10, includes a memory array unit 801 and a memory control unit 820 as its principal parts. The memory array unit 801 is structured to arrange memory elements (memory cells) 802 of a dynamic type in an array. The memory elements 802 severally store information in the state of binary numbers based on a charge holding state and a charge not holding state. The memory control unit 820 is provided between the memory array unit 801 and an external memory control-device 810. The memory control unit 820 controls the reading of information from the memory array unit 801 and the writing of information to the memory array unit 801 in accordance with a command signal and the like from the memory control device 810.
This kind of the memory device (the DRAM 800) has an auto-refresh function for performing a refresh operation on the basis of a refresh request from the external memory control device 810, and a self refresh function for executing a refresh operation automatically at every satisfaction of a set condition, such as every elapse of a predetermined time, every decrease of a held charge quantity under a predetermined value, or the like, after the condition of the memory device has been set by the external memory control device 810.
A refresh operation of a memory device of a dynamic type like a DRAM in a case of the self refresh function is once performed at every elapse of the time of tREF/m, where “tREF” designates a memory holding time and “m” designates the number of addresses necessary for refreshing the whole memory addresses. For example, supposing that tREF=64 [ms] and m=4096, the refresh operation is performed at every elapse of 15.6 [μs].
In many cases, such a self refresh function is generally adopted as a refresh method in a DRAM or the like to be used for electric equipment, such as a personal computer or a mobile telephone, which uses a small-sized battery having a limited capacity as its power source and is needed to hold stored contents for a long time.
Now, because the above-mentioned self refresh function performs amplification of the charges held in the memory cells and the re-writing of the amplified charges to the original memory cells, the performance of the self refresh function needs electric power at the time of the amplification. Consequently, the performance consumes electric power therefor from a power system. Because it is requested for electric equipment such as a personal computer and a mobile telephone to be used without additional charging of a power source such as a battery having a limited capacity for a long time, the self refresh function performed in a DRAM or the like is strongly requested to decrease power consumption at the time of the performance of the function.
Accordingly, in a conventional technique, a method has been proposed. By the method, a mode register 821 is provided in the memory control unit 820 for decreasing the current consumption at the self refresh function, and the self refresh function is performed only to a predetermined memory space in conformity with a control condition set in the mode register 821.
For example, Patent Document 1 proposes an invention by which whether each of the addresses is a using memory space or not is previously stored to all of the addresses of a memory cell array, and refreshing is not performed to the addresses which are not used (not a using memory space). A further concrete aspect thereof is a method by which boundary addresses between a using memory space and a not using memory space in the whole address space are previously stored, and the refreshing is not performed to the not using memory space having the addresses larger than the boundary addresses. However, the conventional invention does not aim the decrease of power consumption as a first primary object, rather aims to prevent the lowering of a processing data rate. Consequently, the technique of this Pat. No. 2,829,998 cannot always achieve the decrease of power consumption.
Alternatively, as another conventional technique for controlling such kind of refresh function, for example, a technique schematically shown in FIGS. 11 and 12 is known. That is, correspondence relations between the contents of the setting of the control method of the mode register 821 storing two-bit information and the memory spaces to which self refreshing is performed are determined in advance. In addition, all of the address spaces are previously divided into a plurality of memory spaces such as a memory space A, a memory space B, a memory space C and a memory space D, and the contents of the mode register 821 is made to be written at the time of the starting of the memory device. Then, for example, in a case where the contents of the mode register 821 is “11”, self refreshing is performed only to the memory space A, a top quarter of the whole memory space of the memory device, and the self refreshing is not performed to the other part of the whole memory space (i.e., the self refreshing at that time is omitted). In such a way, as shown in FIG. 12, only the quarter of the whole address space receives the self refresh operation, the current consumption necessary for the self refresh operation at that time can be decreased to about a quarter of the current consumption necessary for the self refresh operation for the whole address space.
Alternatively, for example, Patent Document 2 proposes a technique for realizing an inexpensive memory having a large memory capacity and a small data holding current by modularizing a DRAM, a static random access memory (SRAM) and a nonvolatile memory device into a package.
[Patent Document 1]: Japanese Patent No. 2829998 (Claims and the Whole Detailed Description of the Invention)
[Patent Document 2]: Japanese Patent Application Laid-Open Publication No. 2001-344967 (Claims and the Whole Detailed Description of the Invention)
However, because the technique proposed by the Patent Document 1 stores whether each address of the whole address of the memory cell array is a using memory space or not, the technique has a problem such that memory means for the storage and means for reading data from the memory means and for discriminating the necessity of refreshment of all of the addresses to control the refreshment operation become very complicated. In addition, because the memory cell array has a tendency to increase its capacity more and more, the number of addresses further increases. Consequently, there is another problem such that the means for storing whether all of the addresses are severally using memory spaces or not to discriminate the addresses is obliged to be complicated more and more.
Moreover, as a further detailed aspect, boundary addresses of using memory spaces and not using memory spaces in the whole address space are previously stored, and refreshment is not performed to not using memory spaces having larger addresses than the boundary addresses. However, by such a method, refreshment is performed to the spaces before the boundary addresses and is not performed to the spaces after the boundary addresses. In such a way, the whole address space can be divided into only two spaces at the boundary addresses as a boundary line. Consequently, for example, the following control cannot be realized: the whole address space is divided into four memory spaces, and only the second memory space and the third memory space of the four spaces from the top are in use and refreshment is performed to the second and the third memory spaces.
Moreover, in the refresh method schematically shown in FIGS. 11 and 12, which may be a variation of such a technique of the invention proposed in the Patent Document 1, the setting of the mode register 821 is performed at the time of turning of its power source or at the time of initialization such as system resetting. Consequently, the refreshing method is effective to a case where the memory space to be stored and held minimally is previously known like a case such as an operating system (OS), but the refreshing method has a problem in which memory spaces cannot be utilized effectively sometimes or the decrease of power consumption cannot be achieved effectively sometimes in a case where the spaces actually necessary to be used vary dependently on the sizes of data to be stored each time such as a user space, because the memory spaces to be actually used become different from the setting at the time of turning on its power source or at the time of initialization such as system resetting.
For example, in a case where refreshment is set to be performed only to the memory space A at the time of initialization, when the quantity of data to be stored becomes large and all of the memory space A is used, and also when the memory space B is tried to be used in such a case, it is set not to perform refreshment to the memory space B, and consequently the memory space B cannot be used in effect.
Furthermore, by the technique according to the invention proposed by the Patent Document 1, in a case where the memory spaces A, C and D are not in use and only the memory space B is in use, the boundary addresses are located at the end of the memory space B, and consequently refreshment is performed also to the memory space A, which is not to be needed to be refreshed actually, in vain. Hence, sufficiently effective decrease of power consumption cannot be achieved by the technique. This situation also applies to the technique shown in FIGS. 11 and 12.
Moreover, the technique proposed by the Patent Document 2 modularizes a DRAM device, an SRAM device, a nonvolatile memory device into a package, but does not perform the decrease of power consumption of each device. Consequently, it is needless to say that the technique cannot, achieve the decrease of power consumption of the memory device of a dynamic type such as the DRAM device. Moreover, because the DRAM device, the SRAM device and the nonvolatile memory device are modularized in one package, there is possibility that the whole configuration thereof becomes very complicated.